R
Platform Flash XL High-Density Configuration and Storage Device
(1)
Table 30: Write AC Characteristics, Write Enable Controlled
Voltage Range
Symbol
Alt
Parameter
Unit
VDDQ
=
VDDQ
=
2.3V to 2.7V
3.0V to 3.6V
TAVAV
TAVLH
TAVWH
TWC Address Valid to Next Address Valid
Address Valid to Latch Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
85
10
50
50
10
0
85
10
50
50
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
Address Valid to Write Enable High
TDVWH
TELLH
TELWL
TELQV
TELKV
TGHWL
TLHAX
TLLLH
TDS Data Valid to Write Enable High
Chip Enable Low to Latch Enable High
TCS Chip Enable Low to Write Enable Low
Chip Enable Low to Output Valid
85
9
85
9
Chip Enable Low to Clock Valid
Output Enable High to Write Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
17
9
17
9
10
0
10
0
(2)
TWHAV
TWHAX
TWHDX
TWHEH
Write Enable High to Address Valid
(2)
TAH Write Enable High to Address Transition
TDH Write Enable High to Input Transition
TCH Write Enable High to Chip Enable High
Write Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Write Enable High to Latch Enable Low
TWPH Write Enable High to Write Enable Low
TWP Write Enable Low to Write Enable High
Output (Status Register) Valid to VPP Low
Output (Status Register) Valid to Write Protect Low
TVPS VPP High to Write Enable High
Write Enable High to VPP Low
0
0
0
0
0
0
(3)
TWHEL
TWHGL
25
0
25
0
(3)
TWHLL
25
25
50
0
25
25
50
0
TWHWL
TWLWH
TQVVPL
TQVWPL
TVPHWH
TWHVPL
TWHWPL
0
0
200
200
200
200
200
200
Write Enable High to Write Protect Low
TWPHWH
Write Protect High to Write Enable High
Min
200
200
ns
Notes:
1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept Low.
3.
T
and T
have this value when reading in the targeted bank or when reading following a Set Configuration Register command.
WHEL
WHLL
System designers should take this timing into account and can insert a software No-Op instruction to delay the first read in the same bank after
issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the
command is a Read Array operation in a different bank and no changes to the Configuration Register are issued, T
and T
are 0 ns.
WHEL
WHLL
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
54
XILINX [ XILINX, INC ]
