R
Platform Flash XL High-Density Configuration and Storage Device
Table 33: Power-Up Timing Characteristics
VDDQ
=
VDDQ
=
2.3V to 2.7V
3.0V to 3.6V
Symbol
Parameter
Unit
Min
60
50
–
Max
Min
60
50
–
Max
(1)
TRWL
READY_WAIT Low driven from the device
READY_WAIT pulse driven from the system
READY_WAIT rise time
–
–
1
–
–
1
μs
ns
μs
TRWLRWH
(2)
TRWRT
TPHRWZ
Time from RP High to when device releases READY_WAIT to high-
impedance state
–
–
5
200
50
–
–
5
200
50
μs
ns
TPLRWL
TRST
Reset Low to READY_WAIT Low
Time required to trigger a device reset when VDD drops below the
maximum VDDPD threshold
15
15
ms
TVDDPOR
VDD ramp rate
0.2
0.2
50
50
0.2
0.2
50
50
ms
ms
TVDQHPOR VDDQ ramp rate
TVHRWZ
Time from VDD/VDDQ POR thresholds to when device releases
READY_WAIT to high-impedance state
5
15
5
15
ms
Notes:
1. Depends on the V /V
operating conditions.
DD DDQ
2. READY_WAIT requires an external pull-up resistor to V
sufficiently strong to ensure a clean Low-to-High transition within less than
DDQ
T
when the READY_WAIT pin is released to a high-impedance state.
RWRT
Ordering Information
X-Ref Target - Figure 35
Example: XCF128X FTG64 C
Device Type
Operating Range
C = Industrial (T = –40°C to +85°C)
A
Package Type
FT64 = 64-ball, Fine-Pitch Thin Ball Grid Array
FTG64 = 64-ball, Fine-Pitch Thin Ball Grid Array, Pb-free
DS617_11_050808
Notes:
1. See the FT64/FTG64 package specifications at http://www.xilinx.com/support/documentation/package_specifications.htm.
Figure 35: Ordering Information
Valid Ordering Combinations
Table 34: Valid Ordering Combinations
XCF128XFTG64C
XCF128XFT64C
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
58
XILINX [ XILINX, INC ]
