R
Platform Flash XL High-Density Configuration and Storage Device
Table 32: Reset and Power-Up AC Characteristics
Symbol
Parameter
Test Condition
During Program
Min
60
Unit
μs
Reset Low to:
TPLWL
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
During Erase
60
μs
TPLEL
TPLGL
TPLLL
Other Conditions
60
60
μs
μs
Reset High to:
TPHWL
TPHEL
TPHGL
TPHLL
Write Enable Low
Chip Enable Low
Output Enable Low
Latch Enable Low
–
(1),(2)
TPLPH
RP Pulse Width
–
–
50
0
ns
TVDHPH
Supply Voltages High to Reset High
μs
Notes:
1. A device reset is possible but not guaranteed if T
2. Sampled only, not 100% tested.
< 50 ns.
PLPH
X-Ref Target - Figure 34
High
W, G, L
E
Low
VDD, VDDQ
TVDHPT
TPLPH
RP
TPHRWZ
TRWRT
TRWL
TRWLRWH
READY_WAIT
TPLRWL
TRWRT
TRWRT
READY_WAIT
(pulse)
Power-Up
Reset
DS617_29_090108
Notes:
1. READY_WAIT requires an external pull-up resistor to V
sufficiently strong to ensure a clean Low-to-High transition within less than T
DDQ
RWRT
when the READY_WAIT pin is released to a high-impedance state.
Figure 34: READY_WAIT AC Waveform
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
57
XILINX [ XILINX, INC ]
