R
Platform Flash XL High-Density Configuration and Storage Device
(1)
Table 31: Write AC Characteristics, Chip Enable Controlled
Voltage Range
Symbol
Alt
Parameter
Unit
VDDQ
=
VDDQ
=
2.3V to 2.7V
3.0V to 3.6V
TAVAV
TAVEH
TAVLH
TDVEH
TEHAX
TEHDX
TEHEL
TEHGL
TEHWH
TELKV
TELEH
TELLH
TELQV
TGHEL
TLHAX
TLLLH
TWC Address Valid to Next Address Valid
Address Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
85
50
10
50
0
85
50
10
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Latch Enable High
TDS Data Valid to Chip Enable High
TAH Chip Enable High to Address Transition
TDH Chip Enable High to Input Transition
TCPH Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
TCH Chip Enable High to Write Enable High
Chip Enable Low to Clock Valid
0
0
25
0
25
0
0
0
9
9
TCP Chip Enable Low to Chip Enable High
Chip Enable Low to Latch Enable High
Chip Enable Low to Output Valid
50
10
85
17
9
50
10
85
17
9
Output Enable High to Chip Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
10
25
0
10
25
0
(2)
TWHEL
Write Enable High to Chip Enable Low
TCS Write Enable Low to Chip Enable Low
Chip Enable High to VPP Low
TWLEL
TEHVPL
TEHWPL
TQVVPL
TQVWPL
TVPHEH
200
200
0
200
200
0
Chip Enable High to Write Protect Low
Output (Status Register) Valid to VPP Low
Output (Status Register) Valid to Write Protect Low Min
0
0
TVPS VPP High to Chip Enable High
Min
200
200
TWPHEH
Write Protect High to Chip Enable High
Min
200
200
ns
Notes:
1. Sampled only, not 100% tested.
2.
T
has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers
WHEL
should take this timing into account and can insert a software No-Op instruction to delay the first read in the same bank after issuing any
command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command
is a Read Array operation in a different bank and no changes to the Configuration Register are issued, T
is 0 ns.
WHEL
X-Ref Target - Figure 33
T
TPLWL
T
TPHWL
W,E,G,L
TPHEL
TPLEL
TPHGL
TPLGL
PHLL
PLLL
RP
TPLPH
TVDHPH
VDD , VDDQ
Power-Up
Reset
DS617_50_090108
Figure 33: Reset and Power-Up AC Waveforms
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
56
XILINX [ XILINX, INC ]
