R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 21
VDD/VDDQ
READY_WAIT
TGLRWH
TRWHAX
G
High
RP
E
L
Low
K
1
2
3
4
TAVRWH
First Address
A22–A0
FFFFh (Sync + Dummy Cycle)
DQ15–DQ0
DS617_16_081309
Figure 21: First Address Latching Sequence (FALS): Clock is Free Running
Table 20: FALS Sequence Timings with Free-Running Clock
Voltage Range
Symbol Parameter
Unit
VDDQ
=
VDDQ
=
2.3V to 2.7V
3.0V to 3.6V
TAVRWH Address Valid before READY_WAIT High
TGLRWH Output Enable Low before READY_WAIT High
TRWHAX Address Hold time after READY_WAIT High
Min
Min
Min
200
200
200
μs
μs
μs
200
4tK + 200(1)
4tK + 200(1)
Notes:
1. 4tK = Fourth rising edge of clock (K) after READY_WAIT goes High.
DS617 (v3.0.1) January 07, 2010
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Product Specification
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XILINX [ XILINX, INC ]
