R
Platform Flash XL High-Density Configuration and Storage Device
Power-On Reset
To ensure a correct power-up sequence of Platform Flash
XL, the V ramp time, T , must not be shorter than
their respective POR thresholds, the READY_WAIT pin is
released after a minimum time of t , to give the power
DD
VDDPOR
RWL
200 μs or longer than 50 ms during power-up (see Figure 18,
page 40). These timing limits correspond to the ramp rate
values for which the power-up current is in the range where
supplies an additional margin for them to stabilize before
initiating the configuration.
For systems using a slow-rising power supply, an additional
power-monitoring circuit can be used to delay the release of
the READY_WAIT pin.
the V ramp time is formally characterized or tested.
DD
The device requires that the V power supply
DD
monotonically rises to the nominal operating voltage within
If the power drops below the power-down threshold
the specified V rise time. If the power supply cannot meet
DD
(V
), the device is reset and the READY_WAIT pin is
DDPD
this requirement, then the device might not perform power-
on reset properly.
held Low again until the POR threshold is reached (see
Figure 18 for an illustration).
During the POR sequence or a reset pulse (RP), the
READY_WAIT pin is held Low by the device. After the
The power-up sequences with and without free-running
clock are represented in Figure 11, page 31 and Figure 17.
required supply voltages (V and V
) have reached
DD
DDQ
X-Ref Target - Figure 17
VDD/VDDQ
TVHRWZ
READY_WAIT
TRWRT
G
L
TAVKH3
TKH3AX
K
1
2
3
4
Latency Cycles (default = 7)
Address not Valid
Valid Address
A22-A0
TKHQV
FFFFh (Sync + Dummy Cycle)
DQ15–DQ0
D0
D1
D2
D3
D4
D5
DS617_13_053008
Notes:
1. W is tied High.
Figure 17: Power-Up Sequence (System with Free-Running Clock)
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
37
XILINX [ XILINX, INC ]
