R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 18
TVDDPOR(MAX)
TVDDPOR(MIN)
Recommended Operating Voltage Range
VDD
Delay FPGA
Configuration(1)
VDDPOR
VDDPD
Time
DS617_14_101608
TVHRWZ
TVHRWZ
TRST
Notes:
1. A slow-ramping V power supply can still be below the minimum operating voltage when the READY_WAIT pin is released. In this case, the
DD
configuration sequence must be delayed until both V and V
have reached their recommended operating conditions.
DD
DDQ
2. For FPGA configuration via Master-BPI mode, the supplies V and V
must reach their respective recommended operating conditions
DD
DDQ
before the start of the FPGA configuration procedure.
Figure 18: V Behavior During the Power-Up Sequence or Brownout
DD
DS617 (v3.0.1) January 07, 2010
Product Specification
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