R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 20
VDD/VDDQ
First Address Latching Sequence
READY_WAIT
G
High
Low
RP
E
L
TGLKH
K
1
2
3
4
TGLKL
TAVKH3
TKH3AX
A22–A0
Address not Valid
First Address
FFFFh (Sync + Dummy Cycle)
DQ15–DQ0
DS617_52_102308
Notes:
1. Only on power-on-reset, FALS is initiated by READY_WAIT rising (Low-to-High) edge or G falling (High-to-Low) edge, whichever occurs last.
After POR, FALS is initiated only by a READY_WAIT rising edge.
Figure 20: First Address Latching Sequence (FALS)
Clock is not Free Running and G Transitions High-to-Low after READY_WAIT Goes High
Table 19: FALS Sequence Timings When the Clock Is Not Free Running
Voltage Range
Symbol
Parameter
Unit
VDDQ
=
VDDQ =
3.0V to 3.6V
2.3V to 2.7V
TAVKH3
TKH3AX
Address setup on third positive edge of clock
Address hold on third positive edge of clock
Min
Min
Min
Min
Min
Min
9
9
ns
ns
ns
ns
ns
ns
9
9
TRWHKL Clock Low after READY_WAIT High
TRWHKH Clock High after READY_WAIT High
600
600
600
600
600
600
600
600
TGLKL
TGLKH
Clock Low after G Low
Clock High after G Low
DS617 (v3.0.1) January 07, 2010
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Product Specification
40
XILINX [ XILINX, INC ]
