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Spartan-3E FPGA Family:
Functional Description
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DS312-2 (v3.8) August 26, 2009
Product Specification
Design Documentation Available
The functionality of the Spartan®-3E FPGA family is now
described and updated in the following documents. The
topics covered in each guide are listed below.
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UG331: Spartan-3 Generation FPGA User Guide
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UG332: Spartan-3 Generation Configuration User
Guide
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Configuration Overview
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Configuration Pins and Behavior
Bitstream Sizes
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
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Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
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Detailed Descriptions by Mode
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Master Serial Mode using Xilinx® Platform Flash
PROM
Master SPI Mode using Commodity SPI Serial Flash
PROM
Master BPI Mode using Commodity Parallel NOR
Flash PROM
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
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I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
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ISE iMPACT Programming Examples
MultiBoot Reconfiguration
For specific hardware examples, please see the Spartan-3E
Starter Kit board web page, which has links to various
design examples and the user guide.
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Spartan-3E Starter Kit Board Page
UG230: Spartan-3E Starter Kit User Guide
Create a Xilinx MySupport user account and sign up to
receive automatic E-mail notification whenever this data
sheet or the associated user guides are updated.
•
Sign Up for Alerts on Xilinx MySupport
© 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS312-2 (v3.8) August 26, 2009
Product Specification
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