R
Functional Description
T
TFF1
D
T1
Q
CE
CK
SR REV
DDR
MUX
TCE
T2
D
Q
TFF2
CE
CK
SR REV
Three-state Path
V
CCO
OFF1
D
O1
Q
CE
CK
OTCLK1
Pull-Up
ESD
ESD
SR REV
DDR
MUX
I/O
Pin
OCE
O2
Program-
Pull-
Down
mable
Output
Driver
Q
D
OFF2
CE
CK
OTCLK2
SR REV
Keeper
Latch
Output Path
Programmable
Delay
I
LVCMOS, LVTTL, PCI
IQ1
Programmable
Delay
Single-ended Standards
using V
REF
D
IDDRIN1
IDDRIN2
Q
V
REF
IFF1
CE
Pin
ICLK1
ICE
CK
SR REV
Differential Standards
I/O Pin
from
Adjacent
IOB
IQ2
D
Q
IFF2
CE
CK
ICLK2
SR REV
SR
REV
Input Path
DS312-2_19_110606
Notes:
1. All IOB control and output path signals have an inverting polarity option wihtin the IOB.
2. IDDRIN1/IDDRIN2 signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
Figure 5: Simplified IOB Diagram
DS312-2 (v3.8) August 26, 2009
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11
Product Specification
XILINX [ XILINX, INC ]
