R
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/05
03/21/05
Initial Xilinx release.
1.1
Added XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs
for CP132 package. Added package markings for QFP packages (Figure 2) and
CP132/CPG132 packages (Figure 4).
11/23/05
03/22/06
11/09/06
2.0
3.0
3.4
Added differential HSTL and SSTL I/O standards. Updated Table 2 to indicate number of
input-only pins. Added Production Stepping information, including example top marking
diagrams.
Upgraded data sheet status to Preliminary. Added XC3S100E in CP132 package and
updated I/O counts for the XC3S1600E in FG320 package (Table 2). Added information
about dual markings for –5C and –4I product combinations to Package Marking.
Added 66 MHz PCI support and links to the Xilinx PCI LogiCORE data sheet. Indicated that
Stepping 1 parts are Production status. Promoted Module 1 to Production status.
Synchronized all modules to v3.4.
04/18/08
08/26/09
3.7
3.8
Added XC3S500E VQG100 package. Added reference to XA Automotive version. Updated
links.
Added paragraph to Configuration indicating the device supports MultiBoot configuration.
Added package sizes to Table 2. Described the speed grade and temperature range
guarantee for devices having a single mark in paragraph 3 under Package Marking.
Deleted Pb-Free Packaging example under Ordering Information. Revised information
under Production Stepping. Revised description of Table 3.
8
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DS312-1 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
