R
Configuration
I/O Capabilities
Spartan-3E FPGAs are programmed by loading configura-
tion data into robust, reprogrammable, static CMOS config-
uration latches (CCLs) that collectively control all functional
elements and routing resources. The FPGA’s configuration
data is stored externally in a PROM or some other non-vol-
atile medium, either on or off the board. After applying
power, the configuration data is written to the FPGA using
any of seven different modes:
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of dif-
ferential I/O pairs available for each device/package combi-
nation.
Spartan-3E FPGAs support the following single-ended
standards:
•
•
3.3V low-voltage TTL (LVTTL)
•
•
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
•
•
3V PCI at 33 MHz, and in some devices, 66 MHz
HSTL I and III at 1.8V, commonly used in memory
applications
•
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
•
•
•
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
•
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
Spartan-3E FPGAs support the following differential stan-
dards:
Furthermore, Spartan-3E FPGAs support MultiBoot config-
uration, allowing two or more FPGA configuration bit-
streams to be stored in a single parallel NOR Flash. The
FPGA application controls which configuration to load next
and when to load it.
•
•
•
•
•
•
•
LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
Package
Size (mm)
Device
VQG100
CPG132
TQG144
PQG208
FTG256
FGG320
FGG400
FGG484
16 x 16
8 x 8
22 x 22
28 x 28
17 x 17
19 x 19
21 x 21
23 x 23
User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff
66
(7)
30
(2)
83
(11)
35
(2)
108
(28)
40
(4)
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
66
(7)
30
(2)
92
(7)
41
(2)
108
(28)
40
(4)
158
(32)
65
(5)
172
(40)
68
(8)
66(3)
(7)
30
(2)
92
(7)
41
(2)
158
(32)
65
(5)
190
(41)
77
(8)
232
(56)
92
(12)
-
-
-
-
-
-
190
(40)
77
(8)
250
(56)
99
(12)
304
(72)
124
(20)
-
-
-
-
-
-
-
-
-
-
-
-
250
(56)
99
(12)
304
(72)
124
(20)
376 156
(82) (21)
XC3S1600E
Notes:
-
-
1. All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4: Pinout Descriptions.
2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
3. The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical
and general references to the VQ100 will apply to the XC3S500E.
DS312-1 (v3.8) August 26, 2009
www.xilinx.com
5
Product Specification
XILINX [ XILINX, INC ]
