R
Functional Description
W
Table 54 shows the connections between the SPI Flash
are not used by the FPGA during configuration. However,
the HOLD pin must be High during the configuration pro-
cess. The PROM’s write protect input must be High in order
to write or program the Flash memory.
PROM and the FPGA’s SPI configuration interface. Each
SPI Flash PROM vendor uses slightly different signal nam-
ing. The SPI Flash PROM’s write protect and hold controls
Table 54: Example SPI Flash PROM Connections and Pin Naming
Silicon
Storage
Atmel
SPI Flash Pin
DATA_IN
FPGA Connection
STMicro
NexFlash Technology
DataFlash
MOSI
DIN
D
Q
S
C
DI
DO
CS
SI
SI
SO
DATA_OUT
SELECT
SO
CSO_B
CCLK
CE#
SCK
CS
CLOCK
CLK
SCK
Not required for FPGA configuration. Must be
High to program SPI Flash. Optional
connection to FPGA user I/O after
configuration.
WR_PROTECT
W
WP
WP#
WP
N/A
W
Not required for FPGA configuration but must
be High during configuration. Optional
connection to FPGA user I/O after
configuration. Not applicable to Atmel
DataFlash.
HOLD
HOLD
HOLD
HOLD#
(see Figure 53)
Only applicable to Atmel DataFlash. Not
required for FPGA configuration but must be
High during configuration. Optional
connection to FPGA user I/O after
configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct
programming of the DataFlash.
RESET
N/A
N/A
N/A
N/A
N/A
N/A
RESET
(see Figure 54)
Only applicable to Atmel DataFlash and only
available on certain packages. Not required
for FPGA configuration. Output from
DataFlash PROM. Optional connection to
FPGA user I/O after configuration.
RDY/BUSY
RDY/BUSY
(see Figure 54)
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
Similarly, the FPGA’s HSWAP pin must be Low to
P
enable pull-up resistors on all user-I/O pins or High to dis-
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
79
Product Specification
XILINX [ XILINX, INC ]
