R
Functional Description
borrowed and returned to the application as general-pur-
pose user I/Os after configuration completes.
Configuration
For additional information on configuration, refer to UG332:
Spartan-3E FPGAs offer several configuration options to
minimize the impact of configuration on the overall system
design. In some configuration modes, the FPGA generates
a clock and loads itself from an external memory source,
either serially or via a byte-wide data path. Alternatively, an
external host such as a microprocessor downloads the
FPGA’s configuration data using a simple synchronous
serial interface or via a byte-wide peripheral-style interface.
Furthermore, multiple-FPGA designs share a single config-
uration memory source, creating a structure called a daisy
chain.
Spartan-3 Generation Configuration User Guide.
Differences from Spartan-3 FPGAs
In general, Spartan-3E FPGA configuration modes are a
superset to those available in Spartan-3 FPGAs. Two new
modes added in Spartan-3E FPGAs provide a glue-less
configuration interface to industry-standard parallel NOR
Flash and SPI serial Flash memories.
Configuration Process
The function of a Spartan-3E FPGA is defined by loading
application-specific configuration data into the FPGA’s
internal, reprogrammable CMOS configuration latches
(CCLs), similar to the way a microprocessor’s function is
defined by its application program. For FPGAs, this configu-
ration process uses a subset of the device pins, some of
which are dedicated to configuration; other pins are merely
Three FPGA pins—M2, M1, and M0—select the desired
configuration mode. The mode pin settings appear in
Table 44. The mode pin values are sampled during the start
of configuration when the FPGA’s INIT_B output goes High.
After the FPGA completes configuration, the mode pins are
available as user I/Os.
Table 44: Spartan-3E Configuration Mode Options and Pin Settings
Master
Serial
SPI
BPI
Slave Parallel
Slave Serial
JTAG
M[2:0] mode pin
settings
<0:0:0>
<0:0:1>
<0:1:0>=Up
<1:1:0>
<1:1:1>
<1:0:1>
<0:1:1>=Down
Data width
Serial
Serial
Byte-wide
Byte-wide
Serial
Serial
Configuration memory
source
Xilinx
Platform
Flash
Industry-standard Industry-standard Any source via
Any source via
Any source via
SPI serial Flash
parallel NOR
Flash or Xilinx
parallel Platform
Flash
microcontroller, microcontroller, microcontroller,
CPU, Xilinx
parallel
CPU, Xilinx
CPU, System
Platform Flash, ACE™ CF, etc.
Platform Flash,
etc.
etc.
Clock source
Internal
oscillator
Internal oscillator Internal oscillator
External clock
on CCLK pin
External clock
on CCLK pin
External clock
on TCK pin
Total I/O pins
borrowed during
configuration
8
13
46
21
8
0
Configuration mode
for downstream
Slave Serial
Slave Serial
Slave Parallel
SlaveParallelor
Memory
Slave Serial
JTAG
daisy-chained FPGAs
Mapped
Possible using
XCFxxP Platform
Flash, which
optionally
generates CCLK
Possible using
XCFxxP Platform
Flash, which
optionally
generates CCLK
Stand-alone FPGA
applications (no
external download
host)
ꢀ
ꢀ
ꢀ
ꢀ
Uses low-cost,
industry-standard
Flash
ꢀ
ꢀ
Supports optional
MultiBoot,
multi-configuration
mode
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
67
Product Specification
XILINX [ XILINX, INC ]
