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Pinout Descriptions
VQ100: 100-lead Very-thin Quad Flat Package
The XC3S100E, XC3S250E, and the XC3S500E devices
are available in the 100-lead very-thin quad flat package,
VQ100. All devices share a common footprint for this pack-
age as shown in Table 131 and Figure 81.
Table 131: VQ100 Package Pinout (Continued)
XC3S100E
XC3S250E
XC3S500E
Pin Name
VQ100
Pin
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Number
P61
P60
P63
P62
P66
P65
P68
P67
P71
P70
P69
P55
P73
P34
P42
P25
P24
P27
P26
P33
P32
P36
P35
P41
P40
P44
P43
P48
P47
P50
P49
P30
P39
P38
Type
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
I/O
Table 131 lists all the package pins. They are sorted by
bank number and then by pin name. Pins that form a differ-
ential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
IO_L03N_1/RHCLK1
IO_L03P_1/RHCLK0
IO_L04N_1/RHCLK3
IO_L04P_1/RHCLK2
IO_L05N_1/RHCLK5
IO_L05P_1/RHCLK4
IO_L06N_1/RHCLK7
IO_L06P_1/RHCLK6
IO_L07N_1
The VQ100 package does not support the Byte-wide
Peripheral Interface (BPI) configuration mode. Conse-
quently, the VQ100 footprint has fewer DUAL-type pins than
other packages.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at:
IO_L07P_1
I/O
http://www.xilinx.com/support/documentation/data_sheets/s3e_pin.zip
IP/VREF_1
VREF
Pinout Table
Table 131 shows the pinout for production Spartan-3E
FPGAs in the VQ100 package.
VCCO_1
VCCO
VCCO_1
VCCO
IO/D5
DUAL
Table 131: VQ100 Package Pinout
IO/M1
DUAL
XC3S100E
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
IO_L07N_2/DIN/D0
IO_L07P_2/M0
DUAL
XC3S250E
XC3S500E
Pin Name
VQ100
Pin
Number
DUAL
Bank
0
Type
I/O
DUAL
IO
P92
P79
P78
P84
P83
P86
P85
P91
P90
P95
P94
P99
P98
P89
P88
P82
P97
P54
P53
P58
P57
DUAL
0
IO_L01N_0
I/O
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
0
IO_L01P_0
I/O
0
IO_L02N_0/GCLK5
IO_L02P_0/GCLK4
IO_L03N_0/GCLK7
IO_L03P_0/GCLK6
IO_L05N_0/GCLK11
IO_L05P_0/GCLK10
IO_L06N_0/VREF_0
IO_L06P_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
0
0
0
0
0
DUAL
0
IO_L08N_2/VS1
DUAL
0
IO_L08P_2/VS2
DUAL
0
IO_L07N_0/HSWAP
IO_L07P_0
DUAL
I/O
IO_L09N_2/CCLK
IO_L09P_2/VS0
DUAL
0
DUAL
0
IP_L04N_0/GCLK9
IP_L04P_0/GCLK8
VCCO_0
GCLK
GCLK
VCCO
VCCO
I/O
IP/VREF_2
VREF
0
IP_L05N_2/M2/GCLK1
DUAL/GCLK
DUAL/GCLK
0
IP_L05P_2/RDWR_B/
GCLK0
0
VCCO_0
1
IO_L01N_1
2
2
3
3
VCCO_2
P31
P45
P3
VCCO
VCCO
I/O
1
IO_L01P_1
I/O
VCCO_2
1
IO_L02N_1
I/O
IO_L01N_3
IO_L01P_3
1
IO_L02P_1
I/O
P2
I/O
DS312-4 (v3.8) August 26, 2009
www.xilinx.com
169
Product Specification
XILINX [ XILINX, INC ]
