R
DC and Switching Characteristics
Speed Grade
Table 92: Timing for the IOB Output Path
-5
-4
Symbol
Description
Conditions
Device
Max
Max
Units
Clock-to-Output Times
(2)
T
When reading from the Output Flip-Flop LVCMOS25 , 12 mA
(OFF), the time from the active transition output drive, Fast slew
at the OCLK input to data appearing at rate
the Output pin
All
2.18
2.50
ns
IOCKP
Propagation Times
(2)
T
The time it takes for data to travel from
the IOB’s O input to the Output pin
LVCMOS25 , 12 mA
All
All
2.24
2.32
2.58
2.67
ns
ns
IOOP
output drive, Fast slew
rate
T
The time it takes for data to travel from
the O input through the OFF latch to the
Output pin
IOOLP
Set/Reset Times
(2)
T
Time from asserting the OFF’s SR input LVCMOS25 , 12 mA
3.27
8.40
3.76
9.65
ns
ns
IOSRP
to setting/resetting data at the Output
pin
output drive, Fast slew
rate
T
Time from asserting the Global Set
Reset (GSR) input on the
IOGSRQ
STARTUP_SPARTAN3E primitive to
setting/resetting data at the Output pin
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 94.
3. For minimum delays use the values reported by the Timing Analyzer.
DS312-3 (v3.8) August 26, 2009
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Product Specification
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