R
DC and Switching Characteristics
I/O Timing
Table 86: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Max
Max
Units
Clock-to-Output Times
(2)
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
T
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global Clock
pin to data appearing at the Output
pin. The DCM is used.
LVCMOS25
,
2.66
3.00
3.01
3.01
3.00
5.60
4.91
4.98
5.36
5.45
2.79
3.45
3.46
3.46
3.45
5.92
5.43
5.51
5.94
6.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ICKOFDCM
12 mA output drive,
Fast slew rate,
(3)
with DCM
(2)
T
When reading from OFF, the time
from the active transition on the
LVCMOS25 ,
ICKOF
12 mA output drive,
Global Clock pin to data appearing at Fast slew rate,
the Output pin. The DCM is not used. without DCM
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 91. If the latter is true, add the appropriate Output adjustment from Table 94.
3. DCM output jitter is included in all measurements.
4. For minimums, use the values reported by the Xilinx timing analyzer.
DS312-3 (v3.8) August 26, 2009
www.xilinx.com
127
Product Specification
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