R
DC and Switching Characteristics
Table 93: Timing for the IOB Three-State Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Max
Max
Units
Synchronous Output Enable/Disable Times
T
T
Time from the active transition at the OTCLK LVCMOS25,
All
1.49
2.70
1.71
3.10
ns
IOCKHZ
IOCKON
input of the Three-state Flip-Flop (TFF) to
when the Output pin enters the
high-impedance state
12 mA output
drive, Fast slew
rate
(2)
Time from the active transition at TFF’s
OTCLK input to when the Output pin drives
valid data
All
All
ns
ns
Asynchronous Output Enable/Disable Times
T
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3E
primitive to when the Output pin enters the
high-impedance state
LVCMOS25,
12 mA output
drive, Fast slew
rate
8.52
9.79
GTS
Set/Reset Times
T
Time from asserting TFF’s SR input to when LVCMOS25,
the Output pin enters a high-impedance state 12 mA output
All
All
2.11
3.32
2.43
3.82
ns
ns
IOSRHZ
drive, Fast slew
Time from asserting TFF’s SR input at TFF to
rate
(2)
T
IOSRON
when the Output pin drives valid data
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 94.
3. For minimum delays use the values reported by the Timing Analyzer.
132
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DS312-3 (v3.8) August 26, 2009
Product Specification
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