R
DC and Switching Characteristics
Inputs and
Table 95: Test Methods for Timing Measurement at I/Os (Continued)
Inputs
Outputs
Outputs
VM (V)
VICM
Signal Standard
(IOSTANDARD)
V
REF (V)
VL (V)
VH (V)
RT (Ω)
50
VT (V)
0.9
DIFF_SSTL18_I
-
-
VREF – 0.5
VREF – 0.5
VREF + 0.5
VREF + 0.5
DIFF_SSTL2_I
50
1.25
VICM
Notes:
1. Descriptions of the relevant symbols are as follows:
V
V
V
– The reference voltage for setting the input switching threshold
– The common mode input voltage
– Voltage of measurement point on signal transition
REF
ICM
M
V – Low-level test voltage at Input pin
L
V
– High-level test voltage at Input pin
H
R – Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required
T
V – Termination voltage
T
2. The load capacitance (C ) at the Output pin is 0 pF for all signal standards.
L
3. According to the PCI specification.
The capacitive load (C ) is connected between the output
and GND. The Output timing for all standards, as published
models are found in the Xilinx development software as well
as at the following link:
L
in the speed files and the data sheet, is always based on a
http://www.xilinx.com/support/download/index.htm
C value of zero. High-impedance probes (less than 1 pF)
L
Delays for a given application are simulated according to its
specific load conditions as follows:
are used for all measurements. Any delay that the test fix-
ture might contribute to test measurements is subtracted
from those measurements to produce the final timing num-
bers as published in the speed files and data sheet.
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 73.
Use parameter values V , R , and V from Table 95.
T
T
M
Using IBIS Models to Simulate Load
Conditions in Application
C
is zero.
REF
2. Record the time to V .
M
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
3. Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
IBIS model (V , R , and V ) correspond directly
REF
REF
MEAS
appropriate IBIS model (including V , R , C
,
REF REF REF
with the parameters used in Table 95 (V , R , and V ). Do
T
T
M
and V
load.
values) or capacitive value to represent the
MEAS
not confuse V
(the termination voltage) from the IBIS
(the input-switching threshold) from the
REF
model with V
REF
4. Record the time to V
.
MEAS
table. A fourth parameter, C , is always zero. The four
REF
parameters describe all relevant output test conditions. IBIS
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
DS312-3 (v3.8) August 26, 2009
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135
Product Specification
XILINX [ XILINX, INC ]
