R
DC and Switching Characteristics
Table 90: Propagation Times for the IOB Input Path
Speed Grade
-5
-4
IFD_
DELAY_
VALUE=
Symbol
Description
Conditions
Device
Max
Max
Units
Propagation Times
(2)
T
The time it takes for data to LVCMOS25
,
0
All
1.96
2.25
ns
IOPLI
travel from the Input pin
through the IFF latch to the
I output with no input delay
programmed
IFD_DELAY_VALUE = 0
(2)
T
The time it takes for data to LVCMOS25
,
2
3
XC3S100E
All Others
5.40
6.30
5.97
7.20
ns
IOPLID
travel from the Input pin IFD_DELAY_VALUE =
through the IFF latch to the default software setting
I output with the input delay
programmed
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 91.
Table 91: Input Timing Adjustments by IOSTANDARD
Table 91: Input Timing Adjustments by IOSTANDARD
Add the
Add the
Adjustment Below
Adjustment Below
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Speed Grade
Speed Grade
-5
-4
Units
-5
-4
Units
Single-Ended Standards
LVTTL
Differential Standards
LVDS_25
0.42
0.42
0
0.43
0.43
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.48
0.39
0.48
0.27
0.48
0.48
0.48
0.30
0.32
0.49
0.39
0.49
0.27
0.49
0.49
0.49
0.30
0.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
BLVDS_25
MINI_LVDS_25
LVPECL_25
0.96
0.62
0.26
0.41
0.41
0.12
0.17
0.30
0.15
0.98
0.63
0.27
0.42
0.42
0.12
0.17
0.30
0.15
RSDS_25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
PCI66_3
HSTL_I_18
HSTL_III_18
SSTL18_I
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 95 and are based on the operating conditions
set forth in Table 77, Table 80, and Table 82.
SSTL2_I
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
130
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DS312-3 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
