R
DC and Switching Characteristics
Speed Grade
Table 88: Setup and Hold Times for the IOB Input Path
-5
-4
IFD_
DELAY_
VALUE=
Symbol
Description
Conditions
Device
Min
Min
Units
Setup Times
TIOPICK
Time from the setup of data at the
LVCMOS25(2)
,
0
All
1.84
2.12
ns
Input pin to the active transition at the IFD_DELAY_VALUE = 0
ICLK input of the Input Flip-Flop
(IFF). No Input Delay is
programmed.
TIOPICKD
Time from the setup of data at the
Input pin to the active transition at the IFD_DELAY_VALUE =
LVCMOS25(2)
,
2
3
XC3S100E
All Others
6.12
6.76
7.01
7.72
ns
IFF’s ICLK input. The Input Delay is
programmed.
default software setting
Hold Times
TIOICKP
Time from the active transition at the LVCMOS25(2)
,
–0.76
–0.76
0
All
ns
ns
IFF’s ICLK input to the point where
data must be held at the Input pin. No
Input Delay is programmed.
IFD_DELAY_VALUE = 0
TIOICKPD
Time from the active transition at the LVCMOS25(2)
,
–3.93
–3.50
–3.93
–3.50
2
3
XC3S100E
All Others
IFF’s ICLK input to the point where
data must be held at the Input pin.
The Input Delay is programmed.
IFD_DELAY_VALUE =
default software setting
Set/Reset Pulse Width
TRPW_IOB Minimum pulse width to SR control
input on IOB
All
1.57
1.80
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 91.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 91. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 89: Sample Window (Source Synchronous)
Symbol
Description
Max
Units
T
Setup and hold capture window of The input capture sample window value is highly specific to a
ps
SAMP
an IOB input flip-flop
particular application, device, package, I/O standard, I/O
placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx application note for application-specific
values.
• XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at
Speeds Up to 666 Mbps
DS312-3 (v3.8) August 26, 2009
www.xilinx.com
129
Product Specification
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