R
DC and Switching Characteristics
Switching Characteristics
All Spartan-3E FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document may be designated as Advance, Preliminary, or
Production, as shown in Table 84. Each category is defined
as follows:
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Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this des-
ignation are considered relatively stable and conservative,
some under-reporting might still occur.
Timing parameters and their representative values are
selected for inclusion below either because they are impor-
tant as general design requirements or they indicate funda-
mental device performance characteristics. The Spartan-3E
speed files (v1.27), part of the Xilinx Development Software,
are the original source for many but not all of the values.
The speed grade designations for these files are shown in
Table 84. For more complete, more precise, and worst-case
data, use the values reported by the Xilinx static timing ana-
lyzer (TRACE in the Xilinx development software) and
back-annotated to the simulation netlist.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family mem-
ber has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
Table 84: Spartan-3E v1.27 Speed Grade Designations
Device
Advance
Preliminary
Production
–MIN, –4, –5
–MIN, –4, –5
–MIN, –4, –5
–MIN, –4, –5
–MIN, –4, –5
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Software Version Requirements
Production-quality systems must use FPGA designs com-
piled using a speed file designated as PRODUCTION sta-
tus. FPGAs designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Advance or Preliminary should not be
used in a production-quality system.
Table 85 provides the history of the Spartan-3E speed files
since all devices reached Production status.
Table 85: Spartan-3E Speed File Version History
ISE
Version Release
Description
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx
ISE software on the FPGA design to ensure that the FPGA
design incorporates the latest timing information and soft-
ware updates.
1.27
1.26
9.2.03i
8.2.02i
Added XA Automotive.
Added -0/-MIN speed grade,
which includes minimum values.
1.25
1.23
1.21
8.2.01i
8.2i
Added XA Automotive devices to
speed file. Improved model for left
and right DCMs.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless other-
wise noted, the published parameter values apply to all
Spartan-3E devices. AC and DC characteristics are
specified using the same numbers for both commercial
and industrial grades.
Updated input setup/hold values
based on default
IFD_DELAY_VALUE settings.
8.1.03i
All Spartan-3E FPGAs and all
speed grades elevated to
Production status.
126
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DS312-3 (v3.8) August 26, 2009
Product Specification
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