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DS123 参数 Datasheet PDF下载

DS123图片预览
型号: DS123
PDF下载: 下载PDF文件 查看货源
内容描述: Platform Flash在系统可编程配置PROM [Platform Flash In-System Programmable Configuration PROMs]
分类和应用: 可编程只读存储器
文件页数/大小: 35 页 / 1019 K
品牌: XILINX [ XILINX, INC ]
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Platform Flash In-System Programmable Configuration PROMs  
AC Characteristics Over Operating Conditions When Cascading  
X-Ref Target - Figure 10  
OE/RESET  
CE  
CLK  
CLKOUT  
(optional)  
T
T
CDF  
CODF  
DATA  
CEO  
Last Bit  
First Bit  
T
OCE  
T
OOE  
T
OCK  
T
COCE  
ds123_23_102203  
XCF01S, XCF02S,  
XCF04S  
XCF08P, XCF16P,  
XCF32P  
Symbol  
Description  
Units  
Min  
Max  
Min  
Max  
CLK to output float delay(2,3)  
when VCCO = 2.5V or 3.3V  
25  
20  
ns  
TCDF  
CLK to output float delay(2,3) when VCCO = 1.8V  
35  
20  
35  
20  
35  
20  
35  
20  
20  
20  
80  
80  
80  
80  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CLK to CEO delay(3,5) when VCCO = 2.5V or 3.3V  
CLK to CEO delay(3,5) when VCCO = 1.8V  
TOCK  
TOCE  
TOOE  
TCOCE  
CE to CEO delay(3,6) when VCCO = 2.5V or 3.3V  
CE to CEO delay(3,6) when VCCO = 1.8V  
OE/RESET to CEO delay(3) when VCCO = 2.5V or 3.3V  
OE/RESET to CEO delay(3) when VCCO = 1.8V  
CLKOUT to CEO delay when VCCO = 2.5V or 3.3V  
CLKOUT to CEO delay when VCCO = 1.8V  
CLKOUT to output float delay  
when VCCO = 2.5V or 3.3V  
25  
25  
ns  
ns  
TCODF  
CLKOUT to output float delay when VCCO = 1.8V  
Notes:  
1. AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.  
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.  
3. Guaranteed by design, not tested.  
4. All AC parameters are measured with V = 0.0V and V = 3.0V.  
IL  
IH  
5. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum period is  
increased based on the CLK to CEO and CE to data propagation delays:  
- T  
- T  
minimum = T  
+ T + FPGA Data setup time  
CYC  
CAC  
OCK CE  
OCK  
maximum = T  
+ T  
CE  
6. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for the  
disable to propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum period is  
increased based on the CE to CEO and CE to data propagation delays:  
- T  
- T  
minimum = T  
+ T  
CYC  
CAC  
OCE CE  
OCK  
maximum = T  
+ T  
CE  
DS123 (v2.18) May 19, 2010  
www.xilinx.com  
Product Specification  
23  
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