R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Speed Grade
-4
-3
Symbol
Description
Device
Min
Max
Min
Max Units
Setup Times - TTL Inputs(1)
TECIK
TPICK
Hold Times
TIKEC Clock Enable (EC) to Clock (IK), no delay
All Other Hold Times
Propagation Delays - TTL Inputs(1)
Clock Enable (EC) to Clock (IK), no delay
All devices
All devices
1.6
1.5
-
-
2.1
2.0
-
-
ns
ns
Pad to Clock (IK), no delay
All devices
All devices
0.0
0.0
-
-
0.9
0.0
-
-
ns
ns
TPID
TPLI
Pad to I1, I2
All devices
All devices
All devices
All devices
-
-
-
-
1.5
2.8
2.7
3.2
-
-
-
-
2.0
3.6
2.8
3.9
ns
ns
ns
ns
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
TIKRI
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
Delay Adder for Input with Delay Option
TDelay
TECIKD = TECIK + TDelay
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
XCS05
XCS10
XCS20
XCS30
XCS40
3.6
3.7
3.8
4.5
5.5
-
-
-
-
-
4.0
4.1
4.2
5.0
5.5
-
-
-
-
-
ns
ns
ns
ns
ns
Global Set/Reset
TMRW Minimum GSR pulse width
TRRI Delay from GSR input to any Q
All devices 11.5
-
13.5
-
ns
ns
ns
ns
ns
ns
XCS05
XCS10
XCS20
XCS30
XCS40
-
-
-
-
-
9.0
-
-
-
-
-
11.3
11.9
12.5
13.1
13.8
9.5
10.0
10.5
11.0
Notes:
1. Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns.
2. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
3. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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DS060 (v1.8) June 26, 2008
Product Specification
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