R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family CLB Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
expressed in nanoseconds unless otherwise noted.
Speed Grade
-4
-3
Description
Symbol
Min
Max
Min
Max
Units
Clocks
TCH
TCL
Clock High time
Clock Low time
3.0
3.0
-
-
4.0
4.0
-
-
ns
ns
Combinatorial Delays
TILO
TIHO
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
-
-
-
1.2
2.0
1.7
-
-
-
1.6
2.7
2.2
ns
ns
ns
THH1O C inputs via H1 via H to X/Y outputs
CLB Fast Carry Logic
TOPCY Operand inputs (F1, F2, G1, G4) to COUT
-
-
-
-
-
1.7
2.8
1.2
2.0
0.5
-
-
-
-
-
2.1
3.7
1.4
2.6
0.6
ns
ns
ns
ns
ns
TASCY
TINCY
TSUM
TBYP
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators
Sequential Delays
TCKO
Clock K to Flip-Flop outputs Q
-
2.1
-
2.8
ns
Setup Time before Clock K
TICK
F/G inputs
1.8
2.9
2.3
1.3
2.0
2.5
-
-
-
-
-
-
2.4
3.9
3.3
2.0
2.6
4.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
TIHCK
F/G inputs via H
THH1CK C inputs via H1 through H
TDICK C inputs via DIN
TECCK C inputs via EC
TRCK
C inputs via S/R, going Low (inactive)
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
0.0
-
0.0
-
ns
TRPW
TRIO
Width (High)
Delay from C inputs via S/R, going High to Q
3.0
-
-
4.0
-
-
ns
ns
3.0
4.0
Global Set/Reset
TMRW
TMRQ
FTOG
Minimum GSR pulse width
11.5
-
13.5
-
ns
Delay from GSR input to any Q
See page 50 for TRRI values per device.
Toggle Frequency (MHz)
-
166
-
125
MHz
(for export control purposes)
44
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DS060 (v1.8) June 26, 2008
Product Specification
XILINX [ XILINX, INC ]
