R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family DC Characteristics Over Operating Conditions
Symbol
Description
Min
Max
-
Units
V
VOH
High-level output voltage @ IOH = –4.0 mA, VCC min
TTL outputs
2.4
High-level output voltage @ IOH = –1.0 mA, VCC min
CMOS outputs
VCC – 0.5
-
V
VOL
Low-level output voltage @ IOL = 12.0 mA, VCC min(1) TTL outputs
-
-
0.4
0.4
-
V
CMOS outputs
V
VDR
Data retention supply voltage (below which configuration data may be lost)
3.0
-
V
ICCO
Quiescent FPGA supply current(2)
Commercial
Industrial
3.0
6.0
+10
10
0.25
-
mA
mA
μA
pF
mA
mA
-
IL
Input or output leakage current
–10
-
CIN
Input capacitance (sample tested)
IRPU
IRPD
Notes:
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.02
0.02
Pad pull-down (when selected) @ VIN = 5V (sample tested)
2. With no output current loads, no active input pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a Tie
option.
Spartan Family Global Buffer Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values where one
global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB
flip-flops are clocked by the global clock net.
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
Speed Grade
-4
Max
2.0
2.4
2.8
3.2
3.5
2.5
2.9
3.3
3.6
3.9
-3
Max
4.0
4.3
5.4
5.8
6.4
4.4
4.7
5.8
6.2
6.7
Symbol
Description
Device
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
Units
ns
TPG
From pad through Primary buffer, to any clock K
ns
ns
ns
ns
TSG
From pad through Secondary buffer, to any clock K
ns
ns
ns
ns
ns
DS060 (v1.8) June 26, 2008
www.xilinx.com
43
Product Specification
XILINX [ XILINX, INC ]
