R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
are expressed in nanoseconds unless otherwise noted.
Speed Grade
-4
-3
Symbol
Single Port RAM
Size(1)
Min
Max
Min
Max
Units
Write Operation
TWCS
TWCTS
TWPS
TWPTS
TASS
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
8.0
8.0
4.0
4.0
1.5
1.5
0.0
0.0
1.5
1.5
0.0
0.0
1.5
1.5
0.0
0.0
-
-
11.6
11.6
5.8
5.8
2.0
2.0
0.0
0.0
2.7
1.7
0.0
0.0
1.6
1.6
0.0
0.0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
TASTS
TAHS
-
-
-
-
TAHTS
TDSS
TDSTS
TDHS
-
-
-
-
-
-
-
-
TDHTS
TWSS
TWSTS
TWHS
TWHTS
TWOS
TWOTS
-
-
WE setup time before clock K
WE hold time after clock K
-
-
-
-
-
-
-
-
Data valid after clock K
6.5
7.0
7.9
9.3
-
-
Read Operation
TRC
TRCT
TILO
Address read cycle time
16x2
32x1
16x2
32x1
16x2
32x1
2.6
3.8
-
-
-
2.6
3.8
-
-
-
ns
ns
ns
ns
ns
ns
Data valid after address change (no Write
Enable)
1.2
2.0
-
1.6
2.7
-
TIHO
TICK
TIHCK
-
-
Address setup time before clock K
1.8
2.9
2.4
3.9
-
-
Notes:
1. Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
DS060 (v1.8) June 26, 2008
www.xilinx.com
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Product Specification
XILINX [ XILINX, INC ]
