R
Spartan and Spartan-XL FPGA Families Data Sheet
Configuration Switching Characteristics
V
CC
RE-PROGRAM
>300 ns
T
POR
PROGRAM
INIT
T
PI
T
ICCK
T
CCLK
CCLK Output or Input
<300 ns
<300 ns
Mode Pins
(Required)
DONE Response
I/O
DS060_33_080400
Master Mode
Symbol
TPOR
TPI
Description
Min
40
Max
130
200
250
2000
250
Units
Power-on reset
ms
Program Latency
30
μs per CLB column
TICCK
TCCLK
TCCLK
CCLK (output) delay
40
μs
ns
ns
CCLK (output) period, slow
CCLK (output) period, fast
640
100
Slave Mode
Symbol
TPOR
TPI
Description
Power-on reset
Min
10
30
4
Max
33
200
-
Units
ms
Program latency
μs per CLB column
TICCK
TCCLK
CCLK (input) delay (required)
CCLK (input) period (required)
μs
80
-
ns
DS060 (v1.8) June 26, 2008
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Product Specification
XILINX [ XILINX, INC ]
