R
Spartan and Spartan-XL FPGA Families Data Sheet
Capacitive Load Factor
3
2
Figure 33 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2.5 ns to the specified delay. If the load capacitance is 20
pF, subtract 0.8 ns from the specified output delay.
Figure 33 is usable over the specified operating conditions
of voltage and temperature and is independent of the output
slew rate control.
1
0
-1
-2
0
20
40
60
80
100
120
140
Capacitance (pF)
DS060_35_080400
Figure 34: Delay Factor at Various Capacitive Loads
48
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DS060 (v1.8) June 26, 2008
Product Specification
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