R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading. For more specific, more pre-
cise, and worst-case guaranteed data, reflecting the actual
routing structure, use the values provided by the static tim-
ing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report.
Spartan Family Output Flip-Flop, Clock-to-Out
Speed Grade
-4
-3
Symbol
Description
Device
Max
Max
Units
Global Primary Clock to TTL Output using OFF
TICKOF
Fast
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
5.3
5.7
8.7
9.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.1
9.3
6.5
9.4
6.8
10.2
11.5
12.0
12.2
12.8
12.8
TICKO
Slew-rate limited
9.0
9.4
9.8
10.2
10.5
Global Secondary Clock to TTL Output using OFF
TICKSOF Fast
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
5.8
6.2
9.2
9.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.6
9.8
7.0
9.9
7.3
10.7
12.0
12.5
12.7
13.2
14.3
TICKSO
Slew-rate limited
9.5
9.9
10.3
10.7
11.0
Delay Adder for CMOS Outputs Option
TCMOSOF Fast
All devices
All devices
0.8
1.5
1.0
2.0
ns
ns
TCMOSO Slew-rate limited
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 33.
3. OFF = Output Flip-Flop
DS060 (v1.8) June 26, 2008
www.xilinx.com
47
Product Specification
XILINX [ XILINX, INC ]
