R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Serial DIN
CCLK
1
2
5
TDCC
TCCD
TCCL
4
TCCH
3
TCCO
Serial DOUT
ds083-3_08_111104
Figure 3: Slave Serial Mode Timing Sequence
CCLK
(Output)
2
TCKDS
TDSCK
1
Serial DIN
Serial DOUT
ds083-3_09_111104
Figure 4: Master Serial Mode Timing Sequence
.
Table 31: Master/Slave Serial Mode Timing Characteristics
Figure
Description
DIN setup/hold, slave mode (Figure 3)
DIN setup/hold, master mode (Figure 4)
DOUT
References
Symbol
TDCC/TCCD
TDSCK/TCKDS
TCCO
Value
Units
ns, min
1/2
1/2
3
5.0/0.0
5.0/0.0
12.0
5.0
ns, min
ns, max
ns, min
High time
4
TCCH
CCLK
Low time
5
TCCL
5.0
ns, min
Maximum start-up frequency
Maximum frequency
FCC_STARTUP
FCC_SERIAL
50
MHz, max
MHz, max
66(1)
Frequency tolerance, master mode with
respect to nominal
+45%
–30%
Notes:
1. If no provision is made in the design to adjust the frequency of CCLK, F
should not exceed F
.
CC_STARTUP
CC_SERIAL
Master/Slave SelectMAP Parameters
Figure 5 is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
Virtex-II Pro Platform FPGA User Guide.
DS031-3 (v3.5) November 5, 2007
Product Specification
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