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DS031 参数 Datasheet PDF下载

DS031图片预览
型号: DS031
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -II FPGA平台:完整的数据表 [Virtex-II Platform FPGAs: Complete Data Sheet]
分类和应用:
文件页数/大小: 318 页 / 2407 K
品牌: XILINX [ XILINX, INC ]
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Virtex-II Platform FPGAs: DC and Switching Characteristics  
IOB Output Switching Characteristics  
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust  
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 14.  
Table 16: IOB Output Switching Characteristics  
Speed Grade  
Description  
Propagation Delays  
Symbol  
Units  
-6  
-5  
-4  
O input to Pad  
TIOOP  
1.43  
1.72  
1.51  
1.83  
1.74  
2.11  
ns, Max  
ns, Max  
O input to Pad via transparent latch  
3-State Delays  
TIOOLP  
T input to Pad high-impedance(1)  
T input to valid data on Pad  
TIOTHZ  
TIOTP  
0.51  
1.38  
0.80  
1.67  
4.73  
0.56  
1.45  
0.88  
1.77  
5.20  
0.64  
1.67  
1.01  
2.04  
5.98  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
T input to Pad high-impedance via transparent latch(1)  
T input to valid data on Pad via transparent latch  
GTS to Pad high impedance(1)  
Sequential Delays  
TIOTLPHZ  
TIOTLPON  
TGTS  
Clock CLK to Pad  
TIOCKP  
TIOCKHZ  
TIOCKON  
1.76  
0.95  
1.82  
1.87  
1.04  
1.94  
2.15  
1.20  
2.22  
ns, Max  
ns, Max  
ns, Max  
Clock CLK to Pad high-impedance (synchronous)(1)  
Clock CLK to valid data on Pad (synchronous)  
Setup and Hold Times Before/After Clock CLK  
O input  
TIOOCK/TIOCKO  
TIOOCECK/TIOCKOCE  
TIOSRCKO/TIOCKOSR  
TIOTCK/TIOCKT  
0.31/–0.08 0.34/–0.09 0.39/–0.11 ns, Min  
0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, Min  
0.27/–0.05 0.30/–0.06 0.34/–0.07 ns, Min  
0.28/–0.06 0.31/–0.07 0.35/–0.08 ns, Min  
0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, Min  
0.27/–0.05 0.30/–0.06 0.34/–0.07 ns, Min  
OCE input  
SR input (OFF)  
3–State Setup Times, T input  
3–State Setup Times, TCE input  
3–State Setup Times, SR input (TFF)  
Set/Reset Delays  
TIOTCECK/TIOCKTCE  
TIOSRCKT/TIOCKTSR  
Minimum Pulse Width, SR input (asynchronous)  
SR input to Pad (asynchronous)  
SR input to Pad high-impedance (asynchronous)(1)  
SR input to valid data on Pad (asynchronous)  
GSR to Pad  
TRPW  
0.61  
2.41  
1.52  
2.39  
5.44  
0.67  
2.59  
1.67  
2.56  
5.98  
0.77  
2.98  
1.92  
2.95  
6.88  
ns, Min  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
TIOSRP  
TIOSRHZ  
TIOSRON  
TIOGSRQ  
Notes:  
1. The 3-state turn-off delays should not be adjusted.  
DS031-3 (v3.5) November 5, 2007  
Product Specification  
www.xilinx.com  
Module 3 of 4  
13  
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