R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)
Speed Grade
IOSTANDARD
Attribute
Timing
Parameter
Description
-6
-5
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDCI, 3.3V, Half-Impedance
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
HSLVDCI_15
T
0.00
0.11
0.42
0.98
0.42
0.52
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.60
0.60
0.58
0.56
0.00
0.11
0.43
1.00
0.42
0.53
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.60
0.60
0.59
0.56
0.00
0.12
0.49
1.14
0.48
0.60
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.40
0.40
0.69
0.69
0.79
0.65
ILVDCI_DV2_33
ILVDCI_DV2_25
ILVDCI_DV2_18
ILVDCI_DV2_15
LVDCI, 2.5V, Half-Impedance
LVDCI, 1.8V, Half-Impedance
LVDCI, 1.5V, Half-Impedance
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI, 1.8V
T
T
T
T
IHSLVDCI_15
IHSLVDCI_18
IHSLVDCI_25
IHSLVDCI_33
HSLVDCI_18
T
HSLVDCI, 2.5V
HSLVDCI_25
T
T
HSLVDCI, 3.3V
HSLVDCI_33
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
GTL_DCI
T
IGTL_DCI
GTLP_DCI
T
IGTLP_DCI
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL, Class II, with DCI
HSTL_I_DCI
T
T
IHSTL_I_DCI
HSTL_II_DCI
IHSTL_II_DCI
IHSTL_III_DCI
HSTL, Class III, with DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL18_I_DCI
SSTL18_II_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
LVDS_25_DCI
LVDS_33_DCI
LVDSEXT_25_DCI
LVDSEXT_33_DCI
T
T
HSTL, Class IV, with DCI
IHSTL_IV_DCI
HSTL, Class I, 1.8V, with DCI
HSTL, Class II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
HSTL, Class IV, 1.8V, with DCI
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL, Class II, 1.8V, with DCI
SSTL, Class I, 2.5V, with DCI
SSTL, Class II, 2.5V, with DCI
SSTL, Class I, 3.3V, with DCI
SSTL, Class II, 3.3V, with DCI
LVDS (Low-Voltage Differential Signaling), 2.5V, with DCI
LVDS, 3.3V, with DCI
T
T
IHSTL_I_DCI_18
IHSTL_II_DCI_18
IHSTL_III_DCI_18
T
T
IHSTL_IV_DCI_18
T
ISSTL18_I_DCI
T
ISSTL18_II_DCI
T
ISSTL2_I_DCI
T
ISSTL2_II_DCI
T
ISSTL3_I_DCI
T
ISSTL3_II_DCI
T
T
ILVDS_25_DCI
ILVDS_33_DCI
LVDSEXT (LVDS Extended Mode), 2.5V, with DCI
LVDSEXT, 3.3V, with DCI
T
T
ILVDSEXT_25_DCI
ILVDSEXT_33_DCI
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see Table 18.
DS031-3 (v3.5) November 5, 2007
Product Specification
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