R
XC3000 Series Field Programmable Gate Arrays
WRITE TO FPGA
WS, CS0, CS1
CS2
1
TCA
2
TCD
TDC
3
D0-D7
CCLK
Valid
4
TWTRB
TBUSY
6
RDY/BUSY
DOUT
D6
D7
Previous Byte
D0
D1
D2
New Byte
X5992
Description
Symbol
Min
Max
Units
Effective Write time required
1
T
100
ns
CA
(Assertion of CS0, CS1, CS2, WS)
DIN Setup time required
DIN Hold time required
2
3
T
T
60
0
ns
ns
DC
CD
WRITE
RDY
RDY/BUSY delay after end of WS
Earliest next WS after end of BUSY
BUSY Low time generated
4
5
6
T
60
9
ns
WTRB
T
0
ns
RBWT
T
2.5
CCLK
BUSY
periods
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the
phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
Note: This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY
will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted
immediately after the end of BUSY.
Figure 28: Peripheral Mode Programming Switching Characteristics
7-30
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
