R
XC3000 Series Field Programmable Gate Arrays
General XC3000 Series Switching Characteristics
4
T
MRW
RESET
2
T
MR
3
T
RM
M0/M1/M2
5
T
PGW
DONE/PROG
6
T
PGI
INIT
(Output)
User State
Clear State
Configuration State
PWRDWN
Note 3
V
CC
(Valid)
V
CCPD
X5387
Description
Symbol
Min
Max
Units
M0, M1, M2 setup time required
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
2
3
4
T
T
1
4.5
6
µs
µs
µs
MR
RM
RESET (2)
T
MRW
Width (Low) required for Re-config.
INIT response after D/P is pulled Low
5
6
T
T
6
µs
µs
PGW
DONE/PROG
7
PGI
PWRDWN (3) Power Down V
V
2.3
V
CC
CCPD
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a
non-monotonically rising VCC may require a >1-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
after Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while VCC >4.0 V(2.5 V for XC3000L).
7-34
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
