R
XC3000 Series Field Programmable Gate Arrays
Program Readback Switching Characteristics
DONE/PROG
(OUTPUT)
1
T
2
RTH
RTRIG (M0)
T
RTCC
4
T
CCL
4
T
CCL
CCLK(1)
5
3
T
CCRD
HI-Z
VALID
READBACK OUTPUT
VALID
READBACK OUTPUT
M1 Input/
RDATA Output
X6116
7
Description
Symbol
Min
250
200
Max
Units
RTRIG
CCLK
RTRIG High
1
T
ns
RTH
RTRIG setup
RDATA delay
High time
2
3
4
5
T
T
T
T
ns
ns
µs
µs
RTCC
CCRD
CCHR
CCLR
100
5
0.5
0.5
Low time
Notes: 1. During Readback, CCLK frequency may not exceed 1 MHz.
2. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins.
3. Readback should not be initiated until configuration is complete.
4. TCCLR is 5 µs min to 15 µs max for XC3000L.
November 9, 1998 (Version 3.1)
7-33
XILINX [ XILINX, INC ]
