R
XC3000 Series Field Programmable Gate Arrays
Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that over-
flows the lead device) on the DOUT pin. There is an inter-
+5 V
+5 V
*
*
*
*
If Readback is
Activated, a
+5 V
+5 V
5-kΩ Resistor is
Required in
M0 M1PWRDWN
M0 M1PWRDWN
M0 M1PWRDWN
Series With M1
CCLK
5 kΩ
5 kΩ
5 kΩ
CCLK
DOUT
CCLK
DOUT
DIN
DOUT
DIN
FPGA
Slave #1
FPGA
Slave #n
M2
...
HDC
M2
HDC
LDC
M2
HDC
LDC
RCLK
A15
A14
A13
A12
A11
A10
A9
A15
A14
A13
A12
A11
A10
A9
General-
Purpose
User I/O
Pins
General-
Purpose
User I/O
Pins
General-
Purpose
User I/O
Pins
EPROM
Other
I/O Pins
Other
I/O Pins
Other
I/O Pins
INIT
INIT
FPGA
Master
D/P
D/P
D7
D6
D5
D4
D3
D2
D1
D0
A8
RESET
Reset
A8
A7
D7
A7
7
A6
D6
D5
D4
D3
D2
D1
D0
A6
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
OE
CE
D/P
RESET
+5 V
INIT
N.C.
5 kΩ Each
8
Open
Reprogram
Collector
System Reset
X5990
Figure 25: Master Parallel Mode Circuit Diagram
November 9, 1998 (Version 3.1)
7-27
XILINX [ XILINX, INC ]
