R
XC3000 Series Field Programmable Gate Arrays
DIN
Bit n
Bit n + 1
1
2
5
T
T
T
CCL
DCC
CCD
CCLK
4
3
T
T
CCH
CCO
DOUT
(Output)
Bit n - 1
Bit n
X5379
Description
Symbol
Min
Max
Units
To DOUT
3
T
100
ns
CCO
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
1
2
4
5
T
T
T
T
60
0
0.05
0.05
ns
ns
µs
µs
MHz
DCC
CCD
CCH
CCL
CCLK
5.0
10
F
CC
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA.
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
Figure 30: Slave Serial Mode Programming Switching Characteristics
7-32
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
