R
XC3000 Series Field Programmable Gate Arrays
A0-A15
Address for Byte n
(output)
Address for Byte n + 1
1
T
RAC
D0-D7
Byte
3
T
2
T
RCD
DRC
RCLK
(output)
7 CCLKs
CCLK
CCLK
(output)
DOUT
(output)
D6
D7
Byte n - 1
X5380
Description
Symbol
Min
Max
Units
To address valid
To data setup
To data hold
RCLK High
1
2
3
T
T
T
T
0
60
0
600
4.0
200
ns
ns
ns
ns
µs
RAC
DRC
RCD
RCH
RCLK
RCLK Low
T
RCL
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics
7-28
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
