R
XC3000 Series Field Programmable Gate Arrays
CCLK
(Output)
T
2
CKDS
T
DSCK
1
Serial Data In
n
n + 1
n + 2
Serial DOUT
(Output)
n – 3
n – 2
n – 1
n
X3223
Description
Data In setup
Data In hold
Symbol
Min
60
0
Max
Units
ns
1
2
T
DSCK
CCLK
C
ns
KDS
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
3. Master-serial-mode timing is based on slave-mode testing.
Figure 24: Master Serial Mode Programming Switching Characteristics
7-26
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
