R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Supported CLB memory configurations and timing modes
for single- and dual-port modes are shown in Table 3.
The selected timing mode applies to both function genera-
tors within a CLB when both are configured as RAM.
XC4000 Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user. Edge-triggered RAM simpli-
fies system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000 Series CLB.
The number of read ports is also programmable:
•
Single Port: each function generator has a common
read and write port
•
Dual Port: both function generators are configured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time is
the same as the logic delay. The write access time is
slightly slower. Both access times are much faster than
any off-chip solution, because they avoid I/O delays.
RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design pro-
cess. Recommended usage is shown in Table 4.
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
Three application notes are available from Xilinx that dis-
cuss edge-triggered RAM: “XC4000E Edge-Triggered and
Dual-Port RAM Capability,” “Implementing FIFOs in
XC4000E RAM,” and “Synchronous and Asynchronous
FIFO Designs.” All three application notes apply to both
XC4000E and XC4000X RAM.
Table 4: RAM Mode Selection
Dual-Port
Level-Sens Edge-Trigg Edge-Trigg
itive
ered
ered
Table 3: Supported RAM Modes
Use for New
Designs?
No
Yes
Yes
16
x
16
x
32
x
Edge-
Triggered Sensitive
Timing
Level-
Size (16x1,
Registered)
1/2 CLB
1/2 CLB
No
1 CLB
Yes
1
2
1
Timing
Simultaneous
Read/Write
Single-Port
Dual-Port
√
√
√
√
√
√
√
No
X
Relative
Performance
2X (4X
effective)
2X
RAM Configuration Options
The function generators in any CLB can be configured as
RAM arrays in the following sizes:
RAM Inputs and Outputs
The F1-F4 and G1-G4 inputs to the function generators act
as address lines, selecting a particular memory cell in each
look-up table.
•
Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
The functionality of the CLB control signals changes when
the function generators are configured as RAM. The
DIN/H2, H1, and SR/H0 lines become the two data inputs
(D0, D1) and the Write Enable (WE) input for the 16x2
memory. When the 32x1 configuration is selected, D1 acts
as the fifth address bit and D0 is the data input.
•
One 32x1 RAM: one data input and one data output.
One F or G function generator can be configured as a 16x1
RAM while the other function generators are used to imple-
ment any function of up to 5 inputs.
Additionally, the XC4000 Series RAM may have either of
two timing modes:
The contents of the memory cell(s) being addressed are
available at the F’ and G’ function-generator outputs. They
can exit the CLB through its X and Y outputs, or can be cap-
tured in the CLB flip-flop(s).
•
Edge-Triggered (Synchronous): data written by the
designated edge of the CLB clock. WE acts as a true
clock enable.
•
Level-Sensitive (Asynchronous): an external WE signal
acts as the write strobe.
Configuring the CLB function generators as Read/Write
memory does not affect the functionality of the other por-
6-12
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
