R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C
• • • C
4
1
EC
D
D
0
WE
1
D
IN
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
4
4
G
• • • G
4
1
1 of 16
LATCH
ENABLE
READ
ADDRESS
WRITE PULSE
D
IN
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
4
F
• • • F
1
4
1 of 16
LATCH
ENABLE
K
READ
ADDRESS
(CLOCK)
WRITE PULSE
X6752
Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
4
C
• • • C
1
4
EC
EC
D /A
D
0
WE
1
4
D
IN
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
G
F
• • • G
• • • F
4
4
1
1
4
4
1 of 16
LATCH
ENABLE
READ
ADDRESS
WRITE PULSE
H'
D
IN
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
4
1 of 16
LATCH
ENABLE
K
READ
ADDRESS
(CLOCK)
WRITE PULSE
X6754
Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
6-14
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
