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5962-9473002MXC 参数 Datasheet PDF下载

5962-9473002MXC图片预览
型号: 5962-9473002MXC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 576 CLBs, 10000 Gates, 90.9MHz, 1368-Cell, CMOS, CPGA223, CERAMIC, PGA-223]
分类和应用: 时钟可编程逻辑
文件页数/大小: 68 页 / 685 K
品牌: XILINX [ XILINX, INC ]
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays  
Dual-Port Edge-Triggered Mode  
Table 6: Dual-Port Edge-Triggered RAM Signals  
In dual-port mode, both the F and G function generators  
are used to create a single 16x1 RAM array with one write  
port and two read ports. The resulting RAM array can be  
read and written simultaneously at two independent  
addresses. Simultaneous read and write operations at the  
same address are also supported.  
RAM Signal  
D
A[3:0]  
CLB Pin  
D0  
F1-F4  
Function  
Data In  
Read Address for F,  
Write Address for F and G  
Read Address for G  
Write Enable  
DPRA[3:0]  
WE  
WCLK  
SPO  
G1-G4  
WE  
K
Clock  
Dual-port mode always has edge-triggered write timing, as  
shown in Figure 3.  
F’  
Single Port Out  
(addressed by A[3:0])  
Dual Port Out  
Figure 6 shows a simple model of an XC4000 Series CLB  
configured as dual-port RAM. One address port, labeled  
A[3:0], supplies both the read and write address for the F  
function generator. This function generator behaves the  
same as a 16x1 single-port edge-triggered RAM array. The  
RAM output, Single Port Out (SPO), appears at the F func-  
tion generator output. SPO, therefore, reflects the data at  
address A[3:0].  
DPO  
G’  
(addressed by DPRA[3:0])  
Note: The pulse following the active edge of WCLK (TWPS  
in Figure 3) must be less than one millisecond wide. For  
most applications, this requirement is not overly restrictive;  
however, it must not be forgotten. Stopping WCLK at this  
point in the write cycle could result in excessive current and  
even damage to the larger devices if many CLBs are con-  
figured as edge-triggered RAM.  
The other address port, labeled DPRA[3:0] for Dual Port  
Read Address, supplies the read address for the G function  
generator. The write address for the G function generator,  
however, comes from the address A[3:0]. The output from  
this 16x1 RAM array, Dual Port Out (DPO), appears at the  
G function generator output. DPO, therefore, reflects the  
data at address DPRA[3:0].  
Single-Port Level-Sensitive Timing Mode  
Note: Edge-triggered mode is recommended for all new  
designs. Level-sensitive mode, also called asynchronous  
mode, is still supported for XC4000 Series backward-com-  
patibility with the XC4000 family.  
6
Therefore, by using A[3:0] for the write address and  
DPRA[3:0] for the read address, and reading only the DPO  
output, a FIFO that can read and write simultaneously is  
easily generated. Simultaneous access doubles the effec-  
tive throughput of the FIFO.  
Level-sensitive RAM timing is simple in concept but can be  
complicated in execution. Data and address signals are  
presented, then a positive pulse on the write enable pin  
(WE) performs a write into the RAM at the designated  
address. As indicated by the “level-sensitive” label, this  
RAM acts like a latch. During the WE High pulse, changing  
the data lines results in new data written to the old address.  
Changing the address lines while WE is High results in spu-  
rious data written to the new address—and possibly at  
other addresses as well, as the address lines inevitably do  
not all change simultaneously.  
The relationships between CLB pins and RAM inputs and  
outputs for dual-port, edge-triggered mode are shown in  
Table 6. See Figure 7 on page 16 for a block diagram of a  
CLB configured in this mode.  
RAM16X1D Primitive  
DPO (Dual Port Out)  
The user must generate a carefully timed WE signal. The  
delay on the WE signal and the address lines must be care-  
fully verified to ensure that WE does not become active  
until after the address lines have settled, and that WE goes  
inactive before the address lines change again. The data  
must be stable before and after the falling edge of WE.  
WE  
WE  
D
Registered DPO  
D
D
Q
DPRA[3:0]  
AR[3:0]  
AW[3:0]  
G Function Generator  
SPO (Single Port Out)  
Registered SPO  
In practical terms, WE is usually generated by a 2X clock. If  
a 2X clock is not available, the falling edge of the system  
clock can be used. However, there are inherent risks in this  
approach, since the WE pulse must be guaranteed inactive  
before the next rising edge of the system clock. Several  
older application notes are available from Xilinx that dis-  
cuss the design of level-sensitive RAMs. These application  
notes include XAPP031, “Using the XC4000 RAM Capabil-  
ity,and XAPP042, “High-Speed RAM Design in XC4000.”  
However, the edge-triggered RAM available in the XC4000  
Series is superior to level-sensitive RAM for almost every  
application.  
WE  
D
Q
D
A[3:0]  
AR[3:0]  
AW[3:0]  
F Function Generator  
WCLK  
X6755  
Figure 6: XC4000 Series Dual-Port RAM, Simple  
Model  
May 14, 1999 (Version 1.6)  
6-15