R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Input Thresholds
Additional Improvements in XC4000X Only
Increased Routing
The input thresholds of 5V devices can be globally config-
ured for either TTL (1.2 V threshold) or CMOS (2.5 V
threshold), just like XC2000 and XC3000 inputs. The two
global adjustments of input threshold and output level are
independent of each other. The XC4000XL family has an
input threshold of 1.6V, compatible with both 3.3V CMOS
and TTL levels.
New interconnect in the XC4000X includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve “Quad
Lines” in each CLB row and column include optional repow-
ering buffers for maximum speed. Additional high-perfor-
mance routing near the IOBs enhances pin flexibility.
Global Signal Access to Logic
Faster Input and Output
There is additional access from global clocks to the F and
G function generator inputs.
A fast, dedicated early clock sourced by global clock buffers
is available for the IOBs. To ensure synchronization with the
regular global clocks, a Fast Capture latch driven by the
early clock is available. The input data can be initially
loaded into the Fast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See “IOB Input Sig-
nals” on page 20 for more information.
Configuration Pin Pull-Up Resistors
During configuration, these pins have weak pull-up resis-
tors. For the most popular configuration mode, Slave
Serial, the mode pins can thus be left unconnected. The
three mode inputs can be individually configured with or
without weak pull-up or pull-down resistors. A pull-down
resistor value of 4.7 kΩ is recommended.
Latch Capability in CLBs
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configu-
ration.
Storage elements in the XC4000X CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up
IOB Output MUX From Output Clock
Like the XC3000A, XC4000 Series devices have “Soft
Start-up.” When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids poten-
tial ground bounce when all outputs are turned on simulta-
neously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
A multiplexer in the IOB allows the output clock to select
either the output data or the IOB clock enable as the output
to the pad. Thus, two different data signals can share a sin-
gle output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive pack-
age. This multiplexer can also be configured as an
AND-gate to implement a very fast pin-to-pin path. See
“IOB Output Signals” on page 23 for more information.
XC4000 and XC4000A Compatibility
Additional Address Bits
Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recompiled
for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.
Larger devices require more bits of configuration data. A
daisy chain of several large XC4000X devices may require
a PROM that cannot be addressed by the eighteen address
bits supported in the XC4000E. The XC4000X Series
therefore extends the addressing in Master Parallel config-
uration mode to 22 bits.
6-8
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
