R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C
• • • C
4
1
EC
D
D
0
WE
1
D
IN
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
4
1 of 16
LATCH
ENABLE
READ
ADDRESS
WRITE PULSE
4
G
• • • G
4
1
D
IN
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
4
F
• • • F
4
1
1 of 16
LATCH
ENABLE
K
READ
ADDRESS
(CLOCK)
WRITE PULSE
X6748
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
Figure 8 shows the write timing for level-sensitive, sin-
gle-port RAM.
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to all zeros, by default.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 7.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Figure 9 and Figure 10 show block diagrams of a CLB con-
figured as 16x2 and 32x1 level-sensitive, single-port RAM.
Table 7: Single-Port Level-Sensitive RAM Signals
RAM Signal
CLB Pin
D0 or D1
Function
Data In
D
Initializing RAM at Configuration
A[3:0]
WE
O
F1-F4 or G1-G4
WE
F’ or G’
Address
Write Enable
Data Out
Both RAM and ROM implementations of the XC4000
Series devices are initialized during configuration. The ini-
tial contents are defined via an INIT attribute or property
T
WC
ADDRESS
T
AS
T
T
WP
AH
T
WRITE ENABLE
DATA IN
T
DH
DS
REQUIRED
X6462
Figure 8: Level-Sensitive RAM Write Timing
6-16
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
