R
XC4000E and XC4000X Series Field Programmable Gate Arrays
The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
ods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configura-
tion data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con-
secutive rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each
daisy-chained device.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
NOTE:
M2 can be shorted to Ground
if not used as I/O
N/C
N/C
4.7 kΩ
M0 M1
M2
M0 M1
CCLK
M2
CCLK
CLOCK
OPTIONAL
DAISY-CHAINED
FPGAs
8
DATA BUS
D
0-7
DIN
DOUT
DOUT
VCC
XC4000E/X
SYNCHRO-
NOUS
XC4000E/X
SLAVE
4.7 kΩ
PERIPHERAL
RDY/BUSY
INIT
CONTROL
SIGNALS
DONE
DONE
INIT
4.7 kΩ
PROGRAM
PROGRAM
PROGRAM
X9027
Figure 56: Synchronous Peripheral Mode Circuit Diagram
6-64
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
