R
XC4000E and XC4000X Series Field Programmable Gate Arrays
A0-A17
(output)
Address for Byte n
Address for Byte n + 1
1
T
RAC
D0-D7
Byte
3
T
2
T
RCD
DRC
RCLK
(output)
7 CCLKs
CCLK
CCLK
(output)
DOUT
(output)
D6
D7
Byte n - 1
X6078
Description
Delay to Address valid
Data setup time
Symbol
Min
Max
200
Units
6
1
2
3
TRAC
TDRC
TRCD
0
60
0
ns
ns
ns
RCLK
Data hold time
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 55: Master Parallel Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-63
XILINX [ XILINX, INC ]
