R
XC4000E and XC4000X Series Field Programmable Gate Arrays
CCLK
INIT
BYTE
0
BYTE
1
BYTE 0 OUT
BYTE 1 OUT
1
0
0
1
2
3
4
5
6
7
DOUT
RDY/BUSY
X6096
Description
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
Symbol
TIC
Min
5
Max
Units
µs
TDC
60
0
ns
6
TCD
ns
CCLK
TCCH
TCCL
FCC
50
60
ns
CCLK Low time
ns
CCLK Frequency
8
MHz
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-65
XILINX [ XILINX, INC ]
