R
XC4000E and XC4000X Series Field Programmable Gate Arrays
The READY/BUSY handshake can be ignored if the delay
from any one Write to the end of the next Write is guaran-
teed to be longer than 10 CCLK periods.
Asynchronous Peripheral Mode
Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of
the logic AND condition of WS and CS0 being Low and RS
and CS1 being High to accept byte-wide data from a micro-
processor bus. In the lead FPGA, this data is loaded into a
double-buffered UART-like parallel-to-serial converter and
is serially shifted into the internal logic.
Status Read
The logic AND condition of the CS0, CS1and RS inputs
puts the device status on the Data bus.
•
•
•
D7 High indicates Ready
D7 Low indicates Busy
D0 through D6 go unconditionally High
The lead FPGA presents the preamble data (and all data
that overflows the lead device) on its DOUT pin. The
RDY/BUSY output from the lead FPGA acts as a hand-
shake signal to the microprocessor. RDY/BUSY goes Low
when a byte has been received, and goes High again when
the byte-wide input buffer has transferred its information
into the shift register, and the buffer is ready to receive new
data. A new write may be started immediately, as soon as
the RDY/BUSY output has gone Low, acknowledging
receipt of the previous data. Write may not be terminated
until RDY/BUSY is High again for one CCLK period. Note
that RDY/BUSY is pulled High with a high-impedance
pull-up prior to INIT going High.
It is mandatory that the whole start-up sequence be started
and completed by one byte-wide input. Otherwise, the pins
used as Write Strobe or Chip Enable might become active
outputs and interfere with the final byte transfer. If this
transfer does not occur, the start-up sequence is not com-
pleted all the way to the finish (point F in Figure 47 on page
53).
In this case, at worst, the internal reset is not released. At
best, Readback and Boundary Scan are inhibited. The
length-count value, as generated by the XACTstep soft-
ware, ensures that these problems never occur.
Although RDY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
one of the data lines. For this purpose, D7 represents the
RDY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.
The length of the BUSY signal depends on the activity in
the UART. If the shift register was empty when the new byte
was received, the BUSY signal lasts for only two CCLK
periods. If the shift register was still full when the new byte
was received, the BUSY signal can be as long as nine
CCLK periods.
Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, M0).
Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
N/C
N/C
N/C
4.7 kΩ
M0
M1
M0
CCLK
DIN
M1
M2
M2
8
DATA
BUS
CCLK
D0–7
OPTIONAL
DAISY-CHAINED
FPGAs
DOUT
DOUT
VCC
ADDRESS
DECODE
LOGIC
CS0
XC4000E/X
ADDRESS
BUS
ASYNCHRO-
NOUS
XC4000E/X
SLAVE
PERIPHERAL
4.7 kΩ
4.7 kΩ
CS1
RS
WS
CONTROL
SIGNALS
RDY/BUSY
INIT
INIT
DONE
DONE
REPROGRAM
PROGRAM
PROGRAM
4.7 kΩ
X9028
Figure 58: Asynchronous Peripheral Mode Circuit Diagram
6-66
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
