R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Configuration Switching Characteristics
T
Vcc
PROGRAM
INIT
POR
RE-PROGRAM
>300 ns
T
PI
T
T
ICCK
CCLK
CCLK OUTPUT or INPUT
<300 ns
M0, M1, M2
(Required)
DONE RESPONSE
I/O
VALID
X1532
<300 ns
Master Modes (XC4000E/EX)
Description
Symbol
TPOR
TPOR
TPI
Min
10
Max
40
Units
ms
M0 = High
M0 = Low
Power-On Reset
Program Latency
40
130
200
ms
30
µs per
CLB column
CCLK (output) Delay
TICCK
TCCLK
TCCLK
40
640
80
250
2000
250
µs
ns
ns
CCLK (output) Period, slow
CCLK (output) Period, fast
Master Modes (XC4000XL)
Description
Symbol
TPOR
TPOR
TPI
Min
10
Max
40
Units
ms
M0 = High
M0 = Low
Power-On Reset
Program Latency
40
130
200
ms
30
µs per
CLB column
CCLK (output) Delay
TICCK
TCCLK
TCCLK
40
540
67
250
1600
200
µs
ns
ns
CCLK (output) Period, slow
CCLK (output) Period, fast
Slave and Peripheral Modes (All)
Description
Power-On Reset
Symbol
TPOR
TPI
Min
10
Max
33
Units
ms
Program Latency
30
200
µs per
CLB column
CCLK (input) Delay (required)
CCLK (input) Period (required)
TICCK
TCCLK
4
µs
100
ns
6-68
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
